1. Field of the Invention
This invention relates to a ring oscillator type voltage controlled oscillator (VCO) particularly for obtaining a wide range oscillation frequency by changing the number of ring oscillator stages.
2. Discussion of the Background
FIG. 1 shows a conventional basic ring oscillator type voltage controlled oscillator (VCO). In the VCO, a plurality of (n) delay elements (voltage controlled delay circuits : VCDs) 11-1 to 11-n whose delay times are variably changed by a control voltage Vcont are cascade-connected. Signals of the output taps of the VCDs 11-1 to 11-n selected by selection signals M1 to Mn are output via respective selection circuits (2-input NAND gates 13-1 to 13-n) after they are inverted by inverters 12-2, . . . , 12-n when the even stages are selected and output via the respective selection circuits as they are when the odd stages are selected. The signals derived via the selection circuits 13-1 to 13-n are supplied to an adder (n-input NAND gate 14) via respective signal lines 15-1 to 15-n and an output signal of the adder 14 is fed back to the input terminal of the first-stage VCD 11-1. At this time, if the number of inverting circuits (inverters or NAND gates for effecting the inverting operation) in the ring oscillator is odd, the feedback loop is a positive feedback loop and the oscillating operation is sustained.
The frequency of an oscillation output Fout output from the NAND gate 14 can be adjusted by the delay time of each VCD stage which is adjusted by the control voltage Vcont and the number of stages of the VCDs 11-1 to 11-n selected by the selection signals M1 to Mn. As shown in FIG. 2, a VCO having a wide variable range can be constructed by superposing the range of the oscillation frequency which can be variably changed by the control voltage Vcont over the range of the oscillation frequency obtained by adjusting the number of VCD stages.
In order to attain the continuous oscillation of the ring oscillator, it is necessary to set the feedback loop of the ring oscillator as a positive feedback loop. For this purpose, when the output signal of one of the even-stage VCDs 11-2, . . . , 11-n is selected, it is necessary to first pass the output through a corresponding one of the inverters 12-2, . . . , 12-n and then input the output to a corresponding one of the selection circuits 13-2, . . . , 13-n so as to always feed back the positive feedback signal to the input terminal of the first-stage VCD 11-1. Therefore, when the number of VCD stages is even, it is necessary to add one inverter to the feedback circuit in comparison with a case of an odd number of VCD stages.
For example, if one VCD stage is added to change the oscillation frequency, the number of inverter circuits in the ring oscillator is not simply increased by one VCD stage, but the inverter is added or not added according to whether the number of VCD stages is even or odd and the number of inverters is irregular. Further, in the case of an even number of stages, the delay time of one stage of the inverter is added in the loop of the ring oscillator. Since the additional delay time of the inverter varies depending on the fluctuation in the manufacturing process, a variation in the power supply voltage and a variation in the temperature, the range of the oscillation frequency which can be varied by the control voltage Vcont and the range of the oscillation frequency obtained by adjusting the number of VCD stages may be deviated from each other. If a deviation between the oscillation frequency ranges occurs, the oscillation frequency cannot be continuously changed. Therefore, in order to prevent occurrence of a deviation between the oscillation frequency ranges, the range (oscillation gain) of the oscillation frequency which can be varied by the control voltage Vcont is increased in the prior art. However, if the oscillation gain is increased, jitters (fluctuation in the frequency) of the oscillation frequency by noises and the fluctuation in the control voltage Vcont are increased and it is not a desirable method.
If the number of VCD stages is selectively changed in n different manners, it is necessary to provide the n-input adder circuit 14 for adding together n delay signals output from the output taps of the VCDs 11-1 to 11-n and n signal lines 15-1 to 15-n for supplying the output signals from the output taps to the adder circuit 14. In this case, if the number n of signals to be added increases, the circuit scale of the adder circuit 14 increases and the delay time occurring in the adder circuit 14 becomes longer. Since the wiring lengths of the n signal lines 15-1 to 15-n from the output taps of the VCDs to the adder circuit 14 are different from one another, the delay times due to the wiring capacitances become different according to the number of VCD stages. Therefore, if the number of VCD stages is changed or the number of switchings of the number of stages is changed, a troublesome operation which is substantially equal to the re-designing for changing the input numbers of the adder circuit 14 and adequately setting the wiring lengths of the signal lines 15-1 to 15-n from the output taps of the VCDs 11-1 to 11-n to the adder circuit 14 is required.
As described above, in the conventional ring oscillator type voltage controlled oscillator, there occurs a problem that the range of the oscillation frequency which can be varied by the control voltage and the range of the oscillation frequency obtained by adjusting the number of VCD stages will be deviated from each other and the oscillation frequency becomes discontinuous. Further, if the range of the oscillation frequency which can be varied by the control voltage is increased in order to solve the above problem, there occurs a new problem that jitters of the oscillation frequency due to noise and a fluctuation in the control voltage are increased.
Further, in the conventional ring oscillator type voltage controlled oscillator, if the number of VCD stages increases, the circuit scale of the adder circuit becomes large and the delay time in the adder circuit becomes long, and the delay times become different because of a difference in the wiring capacitances from the output taps of the VCDs to the adder circuit, and if the number of VCD stages is changed or the number of switchings of the number of stages is changed, there occurs a problem that a troublesome operation substantially equal to the re-designing is required.